Semiconductor device in which bump used for fixing potential of silicon substrate can be easily formed

ABSTRACT

A semiconductor flip chip device having an SOI substrate in which a bump for fixing a potential of a silicon substrate is simply formed a layer (2), including a BOX layer and a silicon layer of the SOI substrate is formed. A semiconductor element selectively is formed on the silicon layer and an interlayer insulation film is then formed on the semiconductor element and the silicon layer. Selectively formed in a silicon nitride film (4) and the layer (2) is a hollow (41) extending from an upper surface of the silicon nitride film (4) to reach an upper surface of the silicon substrate (1). The hollow (41) is formed in an area where the semiconductor element is not formed. The hollow has its side surface defined by the silicon nitride film (4) and the layer (2) and its bottom surface defined by the upper surface of the silicon substrate (1). A bump (5d) made of solder is formed on a part of the upper surface of the silicon substrate (1) defining the bottom surface of the hollow (41). The bump (5d) is provided for fixing the potential of the silicon substrate (1).

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method ofmanufacturing the same, and more particularly to a structure of a flipchip using an SOI (Silicon On Insulator) substrate and a method ofmanufacturing the same.

2. Description of the Background Art

FIGS. 25 through 28 are schematic views for explaining a solderingmethod using a flip chip. FIGS. 25 and 26 are top views and FIGS. 27 and28 are sectional views. Referring to FIG. 25, a plurality of electrodepads 103 made of aluminum are formed on an upper surface of a flip chip100 already undergone dicing. A silicon nitride film 104 is formed on apart of the upper surface of the flip chip 100 where the electrode pads103 are not formed. Referring to FIG. 26, a bump 105 is formed on theelectrode pads 103 of the flip chip 100. Referring to FIG. 27, the flipchip 100 on which the bump 105 is formed is turned upside-down, andthereafter, is mounted on a pattern formed on a wiring substrate 170 bysoldering. Further, as shown in FIG. 28, there is a case where the flipchip 100 is mounted on the wiring substrate 170, and thereafter, issealed with resin 171.

FIG. 29 is a sectional view showing a structure of a conventional flipchip using an SOI substrate. A layer 102 is formed on a siliconsubstrate 101. The layer 102 includes a BOX (Burried Oxide) layer and asilicon layer of the SOI substrate, a semiconductor element selectivelyformed on the silicon layer and an interlayer insulation film formed onthe semiconductor element and the silicon layer. A plurality ofelectrode pads 103 a to 103 d are formed on the layer 102. The electrodepads 103 a to 103 c are electrically connected to the semiconductorelement through a tungsten plug filling a contact hole formed in theinterlayer insulation film and a wiring made of aluminum. The electrodepad 103 d is electrically connected to the silicon substrate 101 througha conductive plug 173 made of polysilicon, tungsten or the like, whichfills a contact hole 172 extending from an upper surface of the layer102 to reach an upper surface of the silicon substrate 101. Furtherformed on the layer 102 is a silicon nitride film 104 patterned so as toexpose the electrode pads 103 a to 103 d. Formed on the electrode pads103 a to 103 d are bumps 105 a to 105 d made of solder, respectively.The bump 105 d is provided for fixing a potential of the siliconsubstrate 101.

FIGS. 30 through 34 are sectional views showing manufacturing steps ofthe conventional flip chip shown in FIG. 29 in sequential order.Referring to FIG. 30, an SOI wafer is prepared first, and after carryingout usual processes of manufacturing a semiconductor, a structure isobtained in which the layer 102 is formed on the silicon substrate 101.Next, referring to FIG. 31, a photoresist 174 having a predeterminedopening pattern is formed on the layer 102 by photolithography. Next,the layer 102 is subjected to anisotropic dry etching using thephotoresist 174 as an etching mask so as to expose a part of the uppersurface of the silicon substrate 101. Thereby formed is the contact hole172 having its side surface defined by the layer 102 and its bottomsurface defined by the upper surface of the silicon substrate 101. Sucha step requires anisotropic dry etching with a very high aspect ratio.

Next, referring to FIG. 32, after removing the photoresist 174, aconductive film 175 made of a polysilicon film, a tungsten film or thelike is formed on an entire surface by CVD method in a thickness thatcan fill the contact hole 172. Next, Referring to FIG. 33, thepolysilicon film 175 is removed by CMP method until an upper surface ofthe layer 102 is exposed. Thereby, the contact hole 172 is filled withthe polysilicon 173. Next, referring to FIG. 34, after forming analuminum film on the layer 102, the aluminum film is patterned, therebyforming the electrode pads 103 a to 103 d at predetermined positions onthe layer 102. The electrode pad 103 d is in contact with thepolysilicon 173.

Subsequently, after forming a silicon nitride film on the entiresurface, the silicon nitride film is patterned, thereby forming thesilicon nitride film 104. Next, after dicing the SOI wafer, the bumps105 a to 105 d are formed on the electrode pads 103 a to 103 d,respectively, thereby obtaining the structure shown in FIG. 29.

In such a conventional flip chip, however, the electrode pad 103 d iselectrically connected to the silicon substrate 101 through thepolysilicon 173 which fills the contact hole 172 formed in the layer102. Accordingly, this requires the steps of: forming the contact hole172 in the layer 102 by anisotropic dry etching with a very high aspectratio (FIG. 31); forming the polysilicon film 175 on the entire surface(FIG. 32); and etching back the polysilicon film 175 by CMP method (FIG.33), resulting in difficulties in the manufacturing steps.

SUMMARY OF THE INVENTION

A first aspect of the present invention is directed to a semiconductordevice. The semiconductor device comprises: an SOI substrate including asemiconductor substrate, an insulation layer formed on a main surface ofthe semiconductor substrate and a semiconductor layer formed on theinsulation layer; a semiconductor element selectively formed on thesemiconductor layer; an interlayer insulation film formed on thesemiconductor element and the semiconductor layer; a first electrode padformed on a main surface of the interlayer insulation film, beingelectrically connected to the semiconductor element; a first bump formedon the first electrode pad; a hollow selectively formed extending fromthe main surface of the interlayer insulation film to reach the mainsurface of the semiconductor substrate; and a second bump formed on thesemiconductor substrate which defines a bottom surface of the hollow.

According to a second aspect of the present invention, the semiconductordevice of the first aspect further comprises a second electrode padformed on the main surface of the semiconductor substrate which definesthe bottom surface of the hollow, wherein the second bump is formed onthe second electrode pad.

According to a third aspect of the present invention, the semiconductordevice of the second aspect further comprises an impurity region formedin the main surface of the semiconductor substrate which defines thebottom surface of the hollow.

A fourth aspect of the present invention is directed to a method ofmanufacturing a semiconductor device. The method comprises the steps of:(a) preparing an SOI substrate including a semiconductor substrate, aninsulation layer formed on a main surface of the semiconductor substrateand a semiconductor layer formed on the insulation layer; (b)selectively forming a semiconductor element on the semiconductor layer;(c) forming an interlayer insulation film on the semiconductor elementand the semiconductor layer; (d) forming a first electrode pad on a mainsurface of the interlayer insulation film, the first electrode pad beingelectrically connected to the semiconductor element; (e) selectivelyforming a hollow which extends from the main surface of the interlayerinsulation film to reach the main surface of the semiconductorsubstrate; and (f) forming a first bump on the first electrode pad and asecond bump on the semiconductor substrate which defines a bottomsurface of the hollow, respectively.

According to a fifth aspect of the present invention, the method of thefourth aspect further comprises the step of (g) forming a secondelectrode pad on the main surface of the semiconductor substrate whichdefines the bottom surface of the hollow, the step (g) being executedafter the step (e) and before the step (f), wherein the second bump isformed on the second electrode pad in the step (f).

According to a sixth aspect of the present invention, in the method ofthe fifth aspect, the steps (d) and (g) are executed by the sameprocess.

According to a seventh aspect of the present invention, the method ofthe fifth or sixth aspect further comprises the step of (h) forming animpurity region in the main surface of the semiconductor substrate whichdefines the bottom surface of the hollow, the step (h) being executedafter the step (e) and before the step (g).

In the semiconductor device according to the first aspect of the presentinvention, the second bump for fixing a potential of the semiconductorsubstrate is formed on a part of the semiconductor substrate definingthe bottom surface of the hollow. This allows simplification ofmanufacturing compared to a type of semiconductor device in which thesecond bump and the semiconductor substrate are brought into electriccontact with each other through polysilicon which fills a contact holereaching the semiconductor substrate.

In the semiconductor device according to the second aspect of thepresent invention, the second bump is formed on the second electrodepad, resulting in improved adhesion of the second bump compared to thecase of forming the second bump directly on the semiconductor substrate.

In the semiconductor device according to the third aspect of the presentinvention, it is possible to reduce a resistance value of thesemiconductor substrate at a position being in contact with the secondelectrode pad.

With the method according to the fourth aspect of the present invention,the second bump for fixing a potential of the semiconductor substrate isformed on a part of the semiconductor substrate defining the bottomsurface of the hollow in the step (f). This allows manufacturing to besimplified compared to a method of manufacturing a semiconductor devicecomprising the steps of: forming a contact hole reaching thesemiconductor substrate; forming a polysilicon film on the entiresurface so as to fill the contact hole; etching back the polysiliconfilm; and forming the second bump on the polysilicon film filling thecontact hole.

With the method according to the fifth aspect of the present invention,the second bump is formed on the second electrode pad, which results inimproved adhesion of the second bump compared to the case of forming thesecond bump directly on the semiconductor substrate.

With the method according to the sixth aspect of the present invention,the second electrode pad can be formed on the main surface of thesemiconductor substrate in the step (g) without adding a specific stepof forming the same.

With the method according to the seventh aspect of the presentinvention, it is possible to reduce a resistance value of thesemiconductor substrate at a position being in contact with the secondelectrode pad.

An object of the present invention is to provide a semiconductor deviceand a method of manufacturing the same, in which a bump for fixing apotential of a silicon substrate can be formed by simplified steps.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view showing a structure of a flip chip accordingto a first preferred embodiment of the present invention;

FIGS. 2 through 13 are sectional views showing steps in sequential orderuntil a silicon nitride film is formed;

FIGS. 14 through 16 are sectional views showing steps in sequentialorder starting at formation of the silicon nitride film until the bumpsare formed;

FIG. 17 is a sectional view showing a structure of a flip chip accordingto a second preferred embodiment of the present invention;

FIGS. 18 through 22 are sectional views showing manufacturing steps ofthe flip chip of the second embodiment in sequential order;

FIG. 23 is a sectional view showing a structure of a flip chip accordingto a third preferred embodiment of the present invention;

FIG. 24 is a sectional view showing a step of a manufacturing method ofthe flip chip of the third embodiment;

FIGS. 25 through 28 are schematic views for explaining a solderingmethod using a flip chip;

FIG. 29 is a sectional view showing a structure of a conventional flipchip; and

FIGS. 30 through 34 are sectional views showing a manufacturing methodof the conventional flip chip in sequential order.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Preferred Embodiment

FIG. 1 is a sectional view showing a structure of a flip chip using anSOI substrate according to a first embodiment. A layer 2 is formed on anupper surface of a silicon substrate 1. The layer 2 includes a BOX layerand a silicon layer of the SOI substrate, a semiconductor elementselectively formed on the silicon layer and an interlayer insulationfilm formed on the semiconductor element and the silicon layer. Aplurality of electrode pads 3 a to 3 c made of aluminum are formed on anupper surface of the layer 2. The electrode pads 3 a to 3 c areelectrically connected to the semiconductor element through a tungstenplug filling a contact hole formed in the interlayer insulation film anda wiring made of aluminum. Further formed on the upper surface of thelayer 2 is a silicon nitride film 4 patterned so as to expose theelectrode pads 3 a to 3 c. Bumps 5 a to 5 c made of solder are formed onthe electrode pads 3 a to 3 c, respectively.

Selectively formed in the silicon nitride film 4 and the layer 2 is ahollow 41 extending from an upper surface of the silicon nitride film 4to reach the upper surface of the silicon substrate 1. The hollow 41 isformed in an area where the semiconductor element is not formed, and hasits side surface defined by the silicon nitride film 4 and the layer 2and its bottom surface defined by the upper surface of the siliconsubstrate 1. A bump 5 d made of solder is formed directly on a part ofthe upper surface of the silicon substrate 1 defining the bottom surfaceof the hollow 41. The bump 5 d is provided for fixing a potential of thesilicon substrate 1.

FIG. 1 is illustrated as if the bump 5 d is formed in a position lowerthan the bumps 5 a to 5 c and there is a difference in steps. However,the bumps 5 a to 5 d have a diameter ranging from 100 to 1000 μm,whereas the sum of thicknesses of the layer 2 and the silicon nitridefilm 4 is the order of several μm (e.g., 3 μm). Therefore, thethicknesses of the layer 2 and the silicon nitride film 4 are so thinthat are negligible compared to the diameter of the bumps 5 a to 5 d.This is actually tantamount to that the bumps 5 a to 5 d are formed withno difference in steps.

FIGS. 2 through 13 are sectional views showing steps in sequential orderuntil the silicon nitride film 4 is formed. Referring to FIG. 2,prepared first is an SOI wafer having a structure in which the siliconsubstrate 1, a BOX layer 6 of about 400 nm thickness and a silicon layer7 of about 200 nm thickness are formed in this order. Next, referring toFIG. 3, a silicon oxide film 8 of about 20 nm thickness and a siliconnitride film 9 of about 200 nm thickness are formed in this orderentirely on an upper surface of the silicon layer 7 by thermal oxidationand CVD method.

Next, referring to FIG. 4, the silicon nitride film 9 and the siliconoxide film 8 are patterned in a predetermined form by photolithographyand anisotropic dry etching. Next, using the remaining part of thesilicon nitride film 9 as an etching mask, the silicon layer 7 issubjected to anisotropic dry etching until the BOX layer 6 is exposed.Thereby formed is a hollow 10 having its bottom surface defined by theBOX layer 6 and its side surface defined by the silicon layer 7. Next,referring to FIG. 5, a silicon oxide film 11 of about 500 nm thicknessis formed on the entire surface by CVD method using plasma of highdensity. Subsequently, the silicon oxide film 11 is etched back by CMP(Chemical Mechanical Polishing) method. The CMP processing stops withthe bottom of the silicon nitride film 9 remained.

Next, referring to FIG. 6, the remaining part of the silicon nitridefilm 9 is removed by wet etching. Then, in order to form a channelregion, an impurity such as boron (in the case of forming NMOS) isimplanted into the silicon layer 7 through the silicon oxide film 8 byion implantation method under the condition of several tens of keV andseveral e12 cm⁻². In the case of forming PMOS, an impurity such asarsenic may be ion implanted under the condition of several hundreds ofkeV and several e12 cm⁻². Next, the silicon oxide film 8 is removed bywet etching. At this time, an upper portion of the silicon oxide film 11is also removed to some extent by the wet etching. Accordingly, anelement isolating insulation film 12 is obtained from the remaining partof the silicon oxide film 11. Next, after forming a silicon oxide film13 of about 5 nm thickness by thermal oxidation, a polysilicon film 14of about 200 nm thickness is formed on the entire surface by CVD method.

Next, referring to FIG. 7, the polysilicon film 14 is patterned byphotolithography and anisotropic dry etching, thereby forming apolysilicon film 15. Next, using the polysilicon film 15 and the elementisolating insulation film 12 as implantation masks, an impurity such asarsenic (in the case of forming NMOS) is implanted into the siliconlayer 7 under the condition of several tens of keV and several e14 cm⁻².Accordingly, a low-concentration region 16 of relatively lowconcentration is formed shallowly in the upper surface of the siliconlayer 7. In the case of forming PMOS, an impurity such as boron fluoridemay be ion implanted under the condition of several tens of keV andseveral e14 cm⁻².

Next, referring to FIG. 8, after forming a silicon oxide film having athickness of about several tens of nm on the entire surface by CVDmethod, the silicon oxide film and the silicon oxide film 13 aresubjected to anisotropic dry etching, thereby forming a sidewall 18 on aside surface of the polysilicon film 15. A part of the silicon oxidefilm 13 serving as an underlying layer of the sidewall 18 is consideredas part of the sidewall 18 and shown integrally with the sidewall 18.Another part of the silicon oxide film 13 serving as an underlying layerof the polysilicon film 15 corresponds to the gate oxide film 17. Next,an impurity such as arsenic (in the case of forming NMOS) is implantedinto the silicon layer 7 through the silicon oxide film 13 by ionimplantation method under the condition of several tens of keV andseveral e15 cm⁻². Thereby formed is a source/drain region 19 ofrelatively high concentration including the low-concentration region 16below the polysilicon film 15. The source/drain region 19 extends fromthe upper surface of the silicon layer 7 to reach an upper surface ofthe BOX layer 6. In the case of forming PMOS, an impurity such as boronfluoride may be ion implanted under the condition of several tens of keVand several e15 cm⁻².

Next, referring to FIG. 9, after forming a cobalt film in a thickness ofabout several nm on the entire surface, heat treatment is performed at atemperature of several hundred degrees for about 1 minutes. Accordingly,silicon and cobalt being in contact with each other react to causesilicidation reaction. As a result, an upper surface of the source/drainregion 19 is silicided to be a cobalt silicide layer 21 while an uppersurface of the polysilicon film 15 is silicided to be a cobalt silicidelayer 20. Thereafter, a part of the cobalt film which has not reactedwith silicon is removed by wet etching.

Next, referring to FIG. 10, after forming a silicon oxide film in athickness of about 1 μm on the entire surface by CVD method, a filmthickness of about several hundreds of nm is removed from an uppersurface of the silicon oxide film by CMP method, thereby forming asilicon oxide film 22 having a planarized upper surface. Next, referringto FIG. 11, a contact hole 23 extending from an upper surface of thesilicon oxide film 22 to reach an upper surface of the silicide layer 21is formed selectively in the silicon oxide film 22 by photolithographyand anisotropic dry etching. Next, after forming a tungsten film ofabout 500 nm thickness on the entire surface by CVD method, the tungstenfilm is removed by CMP method until the upper surface of the siliconoxide film 22 is exposed, thereby forming a tungsten plug 24 which fillsthe contact hole 23. Next, an aluminum wiring 25 in contact with thetungsten plug 24 is formed on the upper surface of the silicon oxidefilm 22.

Next, referring to FIG. 12, the steps shown in FIGS. 10 and 11 arerepeated to form silicon oxide film 26 and 30, contact holes 27 and 31,aluminum wiring 29, and tungsten plugs 28 and 32. Formed on an uppersurface of the silicon oxide film 30 disposed uppermost is an electrodepad 3 made of aluminum (corresponding to the electrode pads 3 a to 3 cshown in FIG. 1) which is in contact with the tungsten plug 32. Next,referring to FIG. 13, a silicon nitride film is formed on the siliconoxide film 30, and the silicon nitride film is patterned to obtain thesilicon nitride film 4.

FIGS. 14 through 16 are sectional views showing steps in sequentialorder starting at formation of the silicon nitride film 4 until thebumps 5 a to 5 d are formed. First, the structure shown in FIG. 14 isobtained through the manufacturing steps shown in FIGS. 2 to 13. Next,referring to FIG. 15, a photoresist 40 having a predetermined openingpattern is formed on the silicon nitride film 4 and the electrode pads 3a to 3 c by photolithography. Then, referring to FIG. 16, using thephotoresist 40 as an etching mask, the silicon nitride film 4 and thelayer 2 are etched in this order by anisotropic dry etching having ahigh etching rate in the direction of depth of the silicon substrate 1until the upper surface of the silicon substrate 1 is exposed. Therebyformed is the hollow 41 having its side surface defined by the siliconnitride film 4 and the layer 2 and its bottom surface defined by theupper surface of the silicon substrate 1.

Next, after removing the photoresist 40, the SOI wafer is subjected todicing. At last, the bumps 5 a to 5 c are formed on the electrode pads 3a to 3 c, respectively, while the bump 5 d is formed on the part of theupper surface of the silicon substrate 1 defining the bottom surface ofthe hollow 41, thereby obtaining the structure shown in FIG. 1. Thebumps 5 a to 5 d may be formed before the step of dicing the SOI wafer.This applies to second and third preferred embodiments to be describedlater.

As has been described, in the flip chip and the manufacturing methodthereof according to the first embodiment, the bump 5 d for fixing apotential of the silicon substrate 1 is formed directly on a part of theupper surface of the silicon substrate 1 exposed by formation of thehollow 41. Therefore, the steps of forming the contact hole 172 (FIG.31), forming the polysilicon film 175 (FIG. 32) and etching back thepolysilicon film 175 (FIG. 33) become unnecessary as in themanufacturing method of the conventional flip chip. This allowssimplification of manufacturing.

Second Preferred Embodiment

FIG. 17 is a sectional view showing a structure of a flip chip accordingto a second embodiment. The layer 2 is formed on the upper surface ofthe silicon substrate 1. Selectively formed in the layer 2 is a hollow51 extending from the upper surface of the layer 2 to reach the uppersurface of the silicon substrate 1. The hollow 51 has its side surfacedefined by the layer 2 and its bottom surface defined by the uppersurface of the silicon substrate 1. The electrode pad 3 d made ofaluminum is formed on a part of the upper surface of the siliconsubstrate 1 defining the bottom surface of the hollow 51. Formed on theupper surface of the layer 2 is the silicon nitride film 4, which isalso formed on the side surface and the bottom surface of the hollow 51.Further, the silicon nitride film 4 is patterned so as to expose theelectrode pads 3 a to 3 d. The bumps 5 a to 5 d are formed on theelectrode pads 3 a to 3 d, respectively. The bump 5 d is electricallyconnected to the silicon substrate 1 through the electrode pad 3 d.

FIGS. 18 through 22 are sectional views showing manufacturing steps ofthe flip chip of the second embodiment in sequential order. First,referring to FIG. 18, the structure in which the layer 2 is formed onthe silicon substrate 1 is obtained by the same method as in the firstembodiment. Next, a photoresist 50 having a predetermined openingpattern is formed on the upper surface of the layer 2 byphotolithography. Next, using the photoresist 50 as an etching mask, thelayer 2 is etched by anisotropic dry etching having a high etching ratein the direction of depth of the silicon substrate 1 until the uppersurface of the silicon substrate 1 is exposed. Formed thereby is thehollow 51 having its side surface defined by the layer 2 and its bottomsurface defined by the upper surface of the silicon substrate 1.

Next, referring to FIG. 19, after removing the photoresist 50, analuminum film 52 having a thickness approximately raging from 500 nm to1 μm is formed on the entire surface by spattering method. The aluminumfilm 52 is also formed on the side surface and the bottom surface of thehollow 51. Next, referring to FIG. 20, a photoresist 53 having apredetermined opening pattern is formed on the aluminum film 52 byphotolithography. Next, using the photoresist 53 as an etching mask, thealuminum film 52 is subjected to anisotropic dry etching, therebyforming the electrode pads 3 a to 3 d.

Next, referring to FIG. 21, after removing the photoresist 53, a siliconnitride film 54 of about 500 nm thickness is formed on the entiresurface by CVD method. Referring to FIG. 22, a photoresist 55 having apredetermined opening pattern is then formed on the silicon nitride film54 by photolithography. Next, using the photoresist 55 as an etchingmask, the silicon nitride film 54 is subjected to anisotropic dryetching, thereby forming the silicon nitride film 4.

Next, after removing the photoresist 55, the SOI wafer is subjected todicing. At last, the bumps 5 a to 5 d are formed on the electrode pads 3a to 3 d, respectively, thereby obtaining the structure shown in FIG.17.

As has been described, in the flip chip and the manufacturing methodthereof according to the second embodiment, the electrode pad 3 d madeof aluminum is formed on the silicon substrate 1 and the bump 5 d isformed on the electrode pad 3 d. This allows improved adhesion betweenthe bump 5 d and the electrode pad 3 d compared to the flip chipaccording to the first embodiment in which the bump 5 d is formeddirectly on the silicon substrate 1.

Further, the electrode pad 3 d is formed in the step of forming theelectrode pads 3 a to 3 c. Thus, formation of the electrode pad 3 d canbe executed without adding a specific step of forming the same.

Third Preferred Embodiment

FIG. 23 is a sectional view showing a structure of a flip chip accordingto a third embodiment. An impurity region 60 of high concentration isformed in the part of the upper surface of the silicon substrate 1defining the bottom surface of the hollow 51. When the silicon substrate1 has a conductivity of p type, the impurity region 60 has aconductivity of p⁺type. The flip chip according to the presentembodiment has the same structure as that of the flip chip of the secondembodiment shown in FIG. 17 except for the impurity region 60.

FIG. 24 is a sectional view showing a step of a manufacturing method ofthe flip chip according to the present embodiment. First, referring toFIG. 24, the structure shown in FIG. 18 is obtained by the same methodas in the second embodiment. Next, using the photoresist 50 as animplantation mask, boron ion 61 is ion implanted into the upper surfaceof the silicon substrate 1 under the condition of several tens of keVand several e15 cm⁻². This allows to form the impurity region 60 ofp⁺type in the part of the upper surface of the silicon substrate 1defining the bottom surface of the hollow 51. Thereafter, the step shownin FIG. 19 follows.

As has been described, in the flip chip and the manufacturing stepthereof according to the present embodiment, the impurity region 60 ofhigh concentration is formed in the part of the upper surface of thesilicon substrate 1 defining the bottom surface of the hollow 51. Thisallows reduction of a resistance value of the silicon substrate 1 at aposition being in contact with the electrode pad 3 d compared to theflip chip according to the second embodiment.

While the invention has been shown and described in detail, theforegoing description is in all aspects illustrative and notrestrictive. It is therefore understood that numerous modifications andvariations can be devised without departing from the scope of theinvention.

What is claimed is:
 1. A semiconductor device comprising: an SOIsubstrate including a semiconductor substrate, an insulation layerformed on a main surface of said semiconductor substrate and asemiconductor layer formed on said insulation layer; a semiconductorelement selectively formed on said semiconductor layer; an interlayerinsulation film formed on said semiconductor element and saidsemiconductor layer; a first electrode pad formed on a main surface ofsaid interlayer insulation film, being electrically connected to saidsemiconductor element; a first bump formed on said first electrode pad;a hollow selectively formed extending from said main surface of saidinterlayer insulation film to reach said main surface of saidsemiconductor substrate; and a second bump formed on said semiconductorsubstrate which defines a bottom surface of said hollow.
 2. Thesemiconductor device according to claim 1, wherein said second bump isformed directly on said main surface of said semiconductor substrate. 3.The semiconductor device according to claim 1 further comprising: asecond electrode pad formed on said main surface of said semiconductorsubstrate which defines said bottom surface of said hollow, wherein saidsecond bump is formed on said second electrode pad.
 4. The semiconductordevice according to claim 3, wherein said second electrode pad is madeof aluminum.
 5. The semiconductor device according to claim 3 furthercomprising an impurity region formed in said main surface of saidsemiconductor substrate which defines said bottom surface of saidhollow.
 6. The semiconductor device according to claim 5, wherein saidimpurity region has an impurity concentration higher than that of saidsemiconductor substrate.